When designing an output buffer, it is important to make sure that the output transistors of the buffer do not turn on at the same time. If the output transistors are on at the same time, a "rush through" current (i.e., a large amount of current pulled directly from Vcc to ground) will produce a high magnitude of noise. To avoid the "rush through" current problem, the timing of the output transistors switching must be matched to ensure that the transistors are not both in saturation at the same time.
Referring to FIG. 1, a diagram of a conventional approach illustrating the effects of a PMOS output transistor and an NMOS output transistor turning on at the same time is shown. If the signals A and B are not matched, the output transistors can both be on at the same time. An equivalent circuit illustrating both transistors conducting and the resulting "rush-through" currents is shown in a box 8.
Referring to FIG. 2, a circuit diagram illustrating a conventional tristate output buffer 10 is shown. The output buffer 10 uses two different logic gates to generate control signals for switching the output transistors. However, matching the delay path of two different logic gates (i.e., a NAND and a NOR) is difficult.
Referring to FIG. 3a, a circuit diagram of a second conventional output buffer 10' is shown. FIG. 3b illustrates resistive and capacitive loads of the circuit 10' of FIG. 3a. The elements in the PMOS driver path are matched through a variable resistive load (i.e., variable across process and corner variations) and associated variable load capacitances (i.e., variable since the voltage level is changing during the transition) to the variable load conditions of the NMOS driver. The turn on of one driver must be matched to the turn off of the complementary driver. In order to mach the turn on of one driver to the turn off of a complementary driver, the timing is generally altered. One conventional way to predictably alter the timing is to build a circuit with fundamentally different timing and then size the PMOS driver (i.e., 2.times. the value of the NMOS driver). However, for various corners and temperatures, the results of such an approach will not be consistent.
Referring to FIG. 4a, a circuit diagram of a third conventional tristate output buffer 10" is shown. FIG. 4b shows an equivalent of circuit 10" with tri-state off. The circuit 10" has similar disadvantages as the circuit 10'.